In 4 layer board designs (typical stack-ups such as signal layer-ground layer-power layer-signal layer), vias serve as the core carriers for interlayer interconnections, facilitating signal, power, and ground continuity between layers. However, constrained by their physical structure, vias cannot achieve ideal conductivity. Their parasitic parameters are essentially derived characteristics from the interaction between conductors and dielectric materials, primarily comprising parasitic resistance (Rv), parasitic inductance (Lv), and parasitic capacitance (Cv). The magnitude of these values is directly related to the via structure, stackup design, and substrate properties.
Parasitic resistance (Rv): Primarily determined by the resistivity of the via conductor material (e.g., copper), the via diameter, and the via length. In 4 layer boards, vias are typically short (conventional stack-up thickness around 1.6mm), with individual via parasitic resistance often in the milliohm range. While negligible when isolated, cumulative resistance in power distribution networks (PDNs) or high-density via arrays can cause significant voltage drops, compromising power supply stability and introducing energy dissipation during signal transmission.
Parasitic Inductance (Lv): This is the most significant parasitic parameter affecting high-frequency signals. Its value correlates positively with the aspect ratio of the via. It can be approximated using the formula Lv≈5.08h[ln(4h/d)+1] (unit: nH, where h is via length and d is via diameter). When vias traverse ground planes or power planes in 4 layer boards, discontinuities in the reference planes further increase equivalent inductance. At high frequencies, this induces abrupt impedance changes that compromise signal integrity.
Parasitic capacitance (Cv): Originating from electric field coupling between the via conductor and adjacent reference planes (ground plane, power plane) as well as other vias. Its magnitude is proportional to the via diameter and pad size, and inversely proportional to the distance between the via and the reference plane. In 4 layer boards, the ground and power planes form parallel planar structures, concentrating via parasitic capacitance. This effect intensifies when high-speed signal vias are adjacent to power planes, further amplifying capacitive coupling.
The Multidimensional Impact of Via Parasitic Parameters on Signal Transmission
The influence of via parasitic parameters on signals exhibits frequency dependency. While negligible at low frequencies, when signal frequencies exceed 1GHz (such as in high-speed serial buses or RF signals), they can trigger a series of signal integrity (SI) issues, potentially compromising system reliability.
Signal Delay and Enhanced Reflection: Parasitic inductance prolongs signal propagation delay while creating impedance discontinuities at via locations. When signals traverse this node, partial energy is reflected back to the source. The superposition of reflected and original signals induces ringing, overshoot, and undershoot phenomena. In high-speed signal paths on 4 layer boards, excessive via parasitic inductance may also cause signal rise/fall times to slow, reducing timing margins and triggering timing errors.
Signal Amplitude Attenuation and Reduced Signal-to-Noise Ratio: Energy dissipation caused by parasitic resistance leads to signal amplitude attenuation over transmission distance. This attenuation is further amplified at high frequencies due to the skin effect (where current concentrates near the conductor surface, effectively increasing resistance). When signal amplitude falls below a threshold, logic misinterpretation may occur at the receiver. Concurrently, noise introduced during attenuation degrades the signal-to-noise ratio (SNR), further compromising signal quality.
Enhanced crosstalk and noise coupling:
As a conduit for signal coupling, parasitic capacitance induces crosstalk between adjacent vias (classified as Near-End Crosstalk NEXT and Far-End Crosstalk FEXT). In 4 layer boards, the parallel structure of ground and power planes forms an ‘electric field shielding cavity’. However, the presence of vias compromises shield integrity, allowing power noise to couple through parasitic capacitance to signal vias, or enabling capacitive coupling between different signal vias to interfere with each other’s transmission, ultimately increasing the system bit error rate.
Coupling effects between power integrity (PI) and signal integrity: Parasitic parameters of power vias and signal vias in 4 layer boards mutually interfere. Parasitic inductance in power vias amplifies power ripple, which couples to signal paths via ground layer capacitance. Conversely, parasitic currents in signal vias affect power stability through the ground plane, creating a vicious cycle between SI and PI.
Optimisation Strategy for Parasitic Parameters Based on 4 layer board Characteristics
Refined Via Structure Design
1.Optimise via size and type: Where routing density permits, appropriately increasing via diameter (e.g., from 0.3mm to 0.5mm) can significantly reduce parasitic resistance and inductance. However, excessive via size must be avoided to prevent undue routing space consumption, particularly in high-density 4 layer boards where via spacing and pad dimensions require careful control. For signals requiring connection between only two adjacent layers, prioritise blind vias (connecting surface and inner layers) or buried vias (connecting two inner layers) over through-holes. This reduces via length by over 50%, substantially lowering parasitic inductance. In high-frequency scenarios, microvias (≤0.15mm diameter) combined with reduced pad dimensions can further decrease parasitic capacitance.
2.Optimising pad and anti-pad design: Larger via pad dimensions increase parasitic capacitance. Therefore, adopt minimal pad designs whilst ensuring soldering reliability. Simultaneously, place anti-pads (Anti-pad) at corresponding via locations on reference planes (ground/power layers) to increase the equivalent distance between vias and reference planes, effectively reducing parasitic capacitance. The anti-pad diameter must be adjusted according to via size and substrate dielectric constant to prevent excessive anti-pads from compromising reference plane integrity.
Layout and Routing Optimisation for 4 layer boards
1.Control via density and spacing: Minimise via count on high-speed signal paths, with no more than two vias per signal trace to avoid cumulative parasitic effects. Spacing between vias, and between vias and signal traces/power planes, must satisfy the ‘3W rule’ (spacing ≥ 3 times trace width). In high-frequency scenarios, this may be increased to 5W to reduce crosstalk caused by capacitive coupling. For power via arrays, adopt a dispersed layout instead of dense packing to reduce equivalent parasitic inductance in the array area.
2.Optimise Signal Routing and Reference Planes: On 4 layer boards, prioritise placing high-speed signals on layers adjacent to the ground plane. This ensures complete return paths and minimises impedance transitions at vias. Avoid crossing reference planes along high-speed signal paths. If crossing is unavoidable, place ground vias near the via to provide the shortest return path, suppressing parasitic inductance and noise coupling.
Enhanced Grounding and Reference Plane Design
1.Implement via-pairing grounding strategy: Configure each high-speed signal via with 1-2 ground vias, maintaining a spacing of ≤3mm between signal and ground vias to form a ‘signal-ground’ pairing structure. This provides low-impedance return paths, reducing parasitic inductance and reflections. At the edges of 4 layer boards or near high-speed signal interfaces, ground via arrays may be deployed to construct shielding walls, suppressing external noise coupling and internal signal leakage.
2.Maintain reference plane integrity: Avoid unnecessary segmentation, gaps, or slots in ground and power planes. If segmentation is required, ensure segmentation lines are perpendicular to high-speed signal paths. Place sufficient ground vias at segmentation points to connect separated regions, minimising impedance discontinuities caused by segmentation. For power planes in 4 layer boards, a combination of grid-pattern ground vias and power vias may be employed to optimise power return paths while suppressing power noise coupling to signals via parasitic parameters.
Simulation-Driven Precision Optimisation
1.Signal Integrity Simulation Validation: During the initial design phase, utilise tools such as HyperLynx or Ansys SIwave to construct a three-dimensional model of the 4 layer board’s vias. Simulate signal transmission characteristics under varying via parameters (diameter, length, pad size) and layout schemes. Quantify the impact of parasitic parameters on signals through metrics such as eye diagrams and S-parameters (insertion loss, return loss), thereby identifying the optimal design solution.
2.Multiphysics Co-simulation: Integrating power integrity simulation with thermal analysis to examine the impact of via parasitics on power supply ripple and component temperature rise. The parasitic resistance of vias in 4 layer boards generates Joule heating under high currents, potentially causing solder joint failure if thermal dissipation is inadequate. Thermal simulation enables optimisation of via placement and quantity, balancing SI, PI, and thermal performance.
3.Process parameter sensitivity analysis: Utilise simulation tools to examine how process parameters—such as substrate dielectric constant, copper thickness, and pad plating (e.g., electroless gold, tin plating)—affect via parasitic characteristics. Combine this with mass production capabilities to identify the most fault-tolerant design, preventing parasitic parameter exceedances due to process variations.
Through refined via design, layout optimisation for 4 layer boards, enhanced ground and reference plane integrity, and precise simulation-driven optimisation, the impact of via parasitics on signal integrity can be effectively mitigated. This approach balances manufacturing costs with system reliability, meeting the design requirements for high-speed 4 layer boards.
