The impedance of an FPC (flexible printed circuit) refers to the electrical resistance encountered by a signal as it travels along the circuit; it is a key indicator of signal transmission quality. It is not a physical barrier, but rather a composite characteristic determined by factors such as the substrate material, trace width and thickness, trace spacing, and the dielectric properties of the substrate. To draw a simple analogy, just as water flowing through a pipe is affected by friction, signals travelling through FPC traces are inevitably subject to this characteristic of impedance.
FPC impedance includes characteristic impedance, differential impedance, odd-mode impedance, even-mode impedance and common-mode impedance. Impedance management is essential during production, so what is the purpose of controlling FPC impedance? There are three main aspects:
1.When installing electronic components via connectors, issues such as electrical conductivity and signal transmission performance must be considered after connection; therefore, the lower the impedance, the better;
2.The materials used in the manufacturing process must ensure low resistivity to guarantee that the overall impedance of the FPC meets product quality requirements and functions correctly;
3.As various signals are transmitted through the conductors, increasing the frequency is necessary to enhance transmission rates. However, variations in the circuit itself—due to factors such as etching, laminate thickness and trace width—can cause fluctuations in impedance values, leading to signal distortion and a decline in the FPC’s performance. Consequently, it is essential to maintain impedance within a specific range.
Factors affecting FPC impedance:
Dielectric constant (DK)
This is the key material property that influences the stability of FPC impedance. The dielectric constant of the FPC substrate directly determines the capacitance during signal transmission; the higher the DK value, the greater the line capacitance and the lower the impedance; conversely, the lower the DK value, the smaller the capacitance and the higher the impedance.
In practical design, the dielectric constant of standard PI substrates typically ranges between 3.2 and 3.5, which meets the requirements of conventional applications; however, in high-frequency scenarios, high-frequency PI substrates with a dielectric constant ≤2.8 should be prioritised. Such substrates exhibit a more stable DK value with minimal fluctuation within the operating temperature range, effectively reducing impedance variations during signal transmission and preventing batch-to-batch impedance discrepancies caused by unstable dielectric constants.
Copper Thickness
There is a clear inverse relationship between copper foil thickness and FPC impedance. The thicker the copper foil, the lower the inductance of the circuit and the lower the impedance; conversely, the thinner the copper foil, the higher the inductance and the higher the impedance. During design, the target impedance value must be matched with an appropriate copper thickness, whilst also considering the feasibility of the manufacturing process—excessively thick copper foil can lead to uneven etching, whilst excessively thin foil may compromise the circuit’s conductivity.
In actual production, we typically select copper foil of standard thickness whilst strictly controlling its uniformity to avoid inconsistencies in impedance within the same batch of FPCs caused by local variations in copper thickness; this is a key detail in ensuring the stability of FPC impedance.
Trace Width and Spacing
These are the factors most easily controlled during the design phase, yet also the most prone to error. Trace width directly affects the resistance and capacitance of the circuit; the wider the trace, the lower the resistance, the higher the capacitance, and the lower the impedance; conversely, the narrower the trace, the higher the resistance, the lower the capacitance, and the higher the impedance. Trace spacing, meanwhile, affects the parasitic capacitance between traces; the closer the spacing, the greater the parasitic capacitance and the lower the impedance; the greater the spacing, the lower the impedance.
During design, professional impedance calculation software such as Polar SI9000 should be utilised in conjunction with the target impedance value (commonly 50Ω for single-ended and 90Ω/100Ω for differential) to precisely calculate the optimal combination of trace width and spacing. At the same time, a process tolerance of ±0.01mm should be allowed for to prevent minor deviations during the etching process from causing the impedance to exceed specifications. For example, when the target impedance is 50Ω and a PI substrate with a dielectric constant of 3.2 is used, a reasonable combination of 0.2mm trace width and 0.2mm trace spacing can be calculated to effectively stabilise the impedance value.
Dielectric Layer Thickness
This has a positive correlation with FPC impedance. The thicker the dielectric layer, the lower the capacitance between the circuit lines and the reference plane, resulting in higher impedance; conversely, the thinner the dielectric layer, the higher the capacitance, leading to lower impedance. During design, the thickness of the dielectric layer must be coordinated with the line width, copper thickness and dielectric constant; it is not possible to adjust any single parameter in isolation.
For example, once the trace width and copper thickness have been determined, if the dielectric layer is too thin, this will result in low impedance. In such cases, the dielectric layer thickness must be appropriately increased to balance the relationship between capacitance and inductance, ensuring that the impedance meets the required standards. At the same time, it is essential to avoid thickness inconsistencies caused by the stacking of multiple dielectric layers, as this would lead to localised impedance deviations and affect overall transmission stability. This is particularly important in high-frequency FPC design, as it directly impacts the effectiveness of controlling impedance fluctuations in high-frequency FPCs.
Methods for Controlling FPC Impedance
Design Stage
Determine the target impedance value for the product (e.g. 50Ω for single-ended circuits and 90Ω/100Ω for differential circuits in standard applications), and select a substrate with the appropriate dielectric constant based on the actual application scenario (standard or high-frequency). Using specialist impedance calculation software such as Polar SI9000, input parameters such as the substrate’s DK value, copper thickness and dielectric layer thickness to precisely calculate the optimal combination of trace width and spacing. At the same time, allow for a process tolerance of ±0.01 mm to prevent minor deviations during subsequent production stages from causing impedance to exceed specifications.
Secondly, optimise routing and stack-up design: for single-ended impedance traces, maintain consistent trace width and avoid abrupt changes; if widening is required, use a gradual transition (length ≥ 5 times the trace width). For differential impedance traces, strictly adhere to the principles of ‘equal length, equal spacing and symmetry’, controlling the ratio of spacing to trace width between 1:1 and 1:2 to minimise phase differences and common-mode interference.
Concurrently, reference ground planes should be appropriately configured to enhance shielding effectiveness and minimise the impact of parasitic capacitance on impedance. In high-frequency applications, a single-layer substrate with a single-layer cover film structure is preferred to avoid thickness inconsistencies caused by the stacking of multiple dielectric layers, thereby reducing local impedance deviations.
Furthermore, impedance traces should be routed away from the edges of the FPC and areas subject to severe bending. Where necessary, impedance compensation traces should be added to counteract the effects of flexural deformation on impedance.
Material Selection Stage
Regarding substrates, standard applications typically use standard PI substrates with a dielectric constant (DK) of 3.2–3.5. For high-frequency applications, high-frequency PI substrates with a DK ≤ 2.8 are preferred. Suppliers with stable dielectric properties must be selected, and DK values and thickness must be sampled and tested for each batch of incoming materials to ensure consistency with design parameters and avoid impedance fluctuations caused by batch variations in the substrate.
The selection of copper foil must be based on the target impedance value. Standard copper foil with uniform thickness should be prioritised to avoid excessive thickness or thinness—excessive thickness can lead to uneven etching, whilst excessive thinness affects conductivity and increases the risk of impedance fluctuations. Additionally, the uniformity of the copper foil must be verified to eliminate localised thickness deviations.
For adhesive-backed FPCs, the thickness and dielectric constant of the adhesive must be controlled; in high-frequency applications, adhesive-free copper-clad laminates should be prioritised to minimise interference with impedance caused by the adhesive.
The cover film must be selected to match the dielectric constant of the substrate, and its thickness must be precisely controlled to prevent variations in circuit capacitance—and consequently, impedance—caused by deviations in the cover film’s thickness.
Furthermore, materials must be stored in sealed, moisture-proof containers, and the production workshop must maintain constant temperature and humidity (23±2°C, 50%±5% RH) to prevent environmental factors from causing substrate shrinkage or expansion, which could in turn affect dielectric properties and impedance stability.
Production Stage
Regarding the etching process, high-precision etching equipment (such as laser direct imaging (LDI) combined with spray etching) must be utilised, and etching parameters must be strictly controlled to prevent over-etching or under-etching—over-etching results in narrower line widths and higher impedance, whilst under-etching leads to wider line widths and lower impedance.
A first-article inspection must be conducted prior to etching to measure the post-etch line width; if the deviation exceeds the tolerance, the etching parameters must be adjusted promptly. Following etching, a 2D measuring instrument is used to inspect the line width to ensure it falls within the design tolerance, whilst simultaneously controlling etching uniformity to prevent line width deviations within the same batch of FPCs.
Regarding the lamination process, regularly calibrate the pressure and temperature of the hot press to ensure uniform thickness of the dielectric layer after lamination. Excessive lamination pressure can lead to thinner substrate and reduced impedance, whilst insufficient pressure results in a thicker substrate and higher impedance. After lamination, use a thickness gauge to measure the dielectric layer thickness; if the deviation exceeds ±5%, adjust the process parameters. Additionally, use uniform shims to prevent localised pressure imbalances.
Surface treatment processes must also be strictly controlled; for example, the thickness of the electroless nickel-gold plating must be maintained within a reasonable range to prevent excessive plating thickness from increasing the effective thickness of the circuit, which would result in low impedance.
Testing and Feedback
During testing, circuits at various locations across the FPC must be covered to ensure that localised impedance deviations are not overlooked. For products that fail testing, the cause must be investigated on a case-by-case basis to determine whether it stems from design parameter deviations, material issues or process fluctuations. Design deviations require recalculation of parameters and revision of the design for prototyping; material issues necessitate a change of batch or supplier; and process fluctuations require adjustments to parameters such as etching and lamination, thereby establishing a closed-loop control system of ‘testing – troubleshooting – optimisation – verification’.
FPC impedance control is a systematic process that spans the entire lifecycle from design and material selection through to production and testing. Only by ensuring every detail at each stage is properly implemented can we effectively guarantee stable and reliable signal transmission, ultimately achieving optimal product performance.
