Unlike traditional substrates such as FR-4, PTFE PCBs have a dielectric constant (Dk) that remains stable between 2.0 and 2.6, with a dielectric loss factor (Df) as low as 0.0005–0.002. Whilst these characteristics give it a natural advantage in high-frequency applications, they also place higher demands on routing precision—PTFE’s low dielectric properties mean that even minute variations in trace width, dielectric thickness and spacing have a far greater impact on impedance than with traditional substrates. Consequently, high-frequency routing on PTFE PCBs is, in essence, a process of ‘precisely matching material properties with routing techniques’, with the core objective being to maintain consistent impedance throughout the circuit and avoid any potential causes of signal distortion.
The foundation of impedance continuity lies in ‘precise impedance design’, rather than blind adjustments made during the routing stage. Impedance calculations for PTFE PCBs must be based on the dielectric parameters of the actual production-grade laminate, rather than theoretical values—this is the core prerequisite for ensuring impedance continuity during subsequent routing, and it is also the most critical distinction between routing PTFE PCBs and FR-4 PCBs.
A common pitfall for many engineers is the tendency to apply the same impedance calculation logic used for FR-4, overlooking the distinct characteristics of PTFE materials, which results in significant discrepancies between design values and actual production values. The correct approach is as follows: first, obtain the measured Dk and Df values for the selected PTFE laminate (Dk values may vary by more than 0.3 between different manufacturers’ modified PTFE composite laminates); then, taking into account the PCB stack-up structure (thicknesses of signal layers, dielectric layers and ground planes), perform impedance modelling using professional field simulation software (such as Polar Si9000 or Cadence Allegro).
In high-frequency applications, the most commonly used impedance types for PTFE PCBs are microstrip (50Ω, 75Ω) and stripline (50Ω). When modelling, three core parameters must be closely monitored: Firstly, the thickness of the PTFE dielectric layer, which is recommended to be controlled between 0.1 and 0.5 mm; a deviation exceeding ±0.01 mm can easily result in an impedance deviation of over 5%.
Secondly, the trace width; for example, for a 50Ω microstrip line on a PTFE PCB with Dk=2.1 and a dielectric thickness of 0.2mm, the trace width is approximately 0.8mm, though this requires fine-tuning based on the actual Dk value; thirdly, the ground plane coverage area; the ground plane beneath the microstrip line must fully cover the trace’s projection, extending at least 1mm beyond the trace’s edges to prevent sudden impedance changes caused by insufficient grounding.
Practical Techniques for High-Frequency Routing
1.Trace Width and Spacing
The low dielectric properties of PTFE PCBs make trace width particularly sensitive—even a slight increase in width causes impedance to drop, whilst a decrease in width causes impedance to rise. Sometimes, a difference of just 0.05 mm can cause impedance to exceed the ±5% tolerance range. Therefore, high-frequency signal traces must maintain a uniform width throughout; there must be no abrupt changes, and they must not alternate between thick and thin sections. Particular attention must be paid to signal input/output points and areas near vias to avoid impedance steps caused by sudden changes in width.
Regarding spacing, it is recommended to strictly adhere to the ‘3W rule’—the spacing between adjacent traces must be ≥3 times the trace width. For differential pairs, the spacing must be fixed, with the distance between differential pairs not less than twice the trace width, to prevent crosstalk from destabilising the impedance. Multiple sets of high-frequency traces should ideally be arranged at equal intervals, which not only reduces mutual interference but also facilitates subsequent impedance testing and debugging.
2.Trace Corners
During high-frequency signal transmission, corners are a ‘high-risk area’ for sudden changes in impedance. Right-angled corners increase the equivalent width of the trace, causing a sudden drop in impedance whilst generating signal reflections and electromagnetic radiation—in the millimetre-wave band (>30 GHz), this effect is amplified several times over. As PTFE PCBs have low inherent loss, the impact of signal reflections is even more pronounced; if corners are poorly designed, signal attenuation will be exacerbated.
For high-frequency routing on PTFE PCBs, it is best to use rounded corners for transitions. The recommended radius for the rounded corner should be 1.5 to 2 times the trace width; under no circumstances should right angles or acute angles be used. If board space is limited and a large-radius rounded corner is not feasible, use a 45° chamfered transition (ensuring the chamfer angle is no less than 45°) to minimise the magnitude of the impedance change. The key is that the trace width at corners must remain constant; the corner design must not cause the trace to widen or narrow.
Particular care must be taken with differential pair corners—they must be symmetrical, with both differential traces being of equal length and the corner angles being identical. Otherwise, any asymmetry in the differential pairs will cause an impedance imbalance, compromising the integrity of the differential signal.
3.Via Design
Vias are the most easily overlooked points of impedance discontinuity in high-frequency routing on PTFE PCBs. The via diameter, pad size and wall thickness all affect impedance continuity. Particularly where high-frequency signal layers connect to ground or power planes, poor via design can lead to signal reflection and insertion loss.
When designing vias for PTFE PCBs, it is advisable to strictly adhere to three principles: Firstly, keep vias as small as possible; in high-frequency applications, prioritise microvias (hole diameter 0.1–0.2 mm) to minimise the impact of vias on trace impedance whilst reducing signal radiation loss; Second, ensure appropriate pad dimensions. The pad diameter should ideally be 2–2.5 times the via diameter, with a clearance of at least 0.1 mm between the pad edge and the trace edge to prevent abrupt impedance changes caused by excessively large pads; Third, incorporate additional ground vias. Arrange ground vias uniformly around signal vias (spacing should not exceed 2 mm) to form a ground shield, thereby reducing signal reflection and minimising crosstalk.
4.Layer Stack Design
The layer stack design of PTFE PCBs directly affects impedance stability and signal integrity. In high-frequency applications, a well-designed layer stack can effectively minimise impedance variations whilst reducing electromagnetic interference. Unlike FR-4, the layer stack of PTFE PCBs must take into account its low-dielectric and low-loss characteristics, with a particular emphasis on ‘ground continuity’ and ‘signal isolation’.
It is recommended to adopt a symmetrical layer stack structure of “signal layer – dielectric layer – ground layer”. High-frequency signal layers should be positioned as close as possible to the ground layer, with the dielectric layer made of PTFE material. An isolation layer (also made of PTFE material) should be inserted between the power layer and the signal layer to prevent power supply noise from interfering with high-frequency signals. If the board has multiple signal layers, the thickness of the dielectric layer between adjacent signal layers should not be less than 0.1 mm, and a ground layer should be inserted in between to reduce crosstalk.
The ground layer must remain intact; under no circumstances should “ground islands” (i.e. the ground layer being divided into isolated sections) be created—this would increase ground impedance, impair signal return paths, and disrupt impedance continuity. If layout constraints necessitate the division of the ground plane, use copper jumpers to connect the various ground regions, ensuring ground continuity and minimising sudden changes in ground impedance.
5.Routing Topology
The longer the transmission path for high-frequency signals, the higher the probability of impedance changes and the greater the signal loss. Therefore, when routing high-frequency signals on PTFE PCBs, the ‘shortest path’ principle must be strictly adhered to: take the shortest route where possible, keep the path straight where possible, and minimise unnecessary bends and branches.
Single-ended signals should ideally run in a straight line; if a bend is unavoidable, the bending radius must be greater than five times the trace width, and the length of the bend must not exceed 1/20th of the signal wavelength (where the high-frequency signal wavelength λ = c/(f × Dk), where c is the speed of light, f is the signal frequency, and Dk is the dielectric constant of PTFE), to avoid impedance fluctuations caused by the bend. Differential signals require even greater care—the lengths of the two traces must be identical (with a deviation of no more than 0.5 mm), and the routing paths must be symmetrical. There must be no branches or asymmetrical bends to ensure differential impedance continuity.
Furthermore, high-frequency signal traces should be routed as far as possible from interference sources such as power connectors and heat sinks to prevent electromagnetic interference from destabilising the impedance. If such interference cannot be avoided, insert a shielding strip (using a grounded copper strip) between the signal trace and the interference source to minimise the impact of interference.
Post-Routing Testing and Optimisation
Completing the routing design does not guarantee stable impedance continuity—the manufacturing processes of PTFE PCBs (etching, lamination, drilling) inevitably introduce some deviation, which may cause the actual impedance to deviate from the design value. Therefore, it is essential to verify impedance continuity using professional testing methods after routing. Any issues must be optimised promptly to ensure the PCB meets the requirements of high-frequency applications.
A commonly used testing method is Time Domain Reflectometry (TDR), which determines whether impedance is continuous by measuring the reflection coefficient of signals on the PTFE PCB traces. During testing, test points must be marked on the PCB sample, covering critical locations such as signal input/output terminals, vias and corners to ensure comprehensive testing. If impedance deviations exceeding the permissible range (±5%) are detected, targeted optimisations can be implemented:
Is the impedance too high? Appropriately widen the trace width (adjusting by 0.02 mm at a time) or increase the thickness of the PTFE dielectric layer to reduce the impedance;
Is the impedance too low? Appropriately narrow the trace width or reduce the thickness of the dielectric layer to increase the impedance;
Abrupt impedance changes at vias? Optimise via dimensions, add more ground vias, or adjust pad sizes;
Abnormal impedance at corners? Increase the fillet radius or adjust the corner angle to reduce impedance fluctuations.
High-frequency routing on PTFE PCBs, put simply, is about striking a balance between signal integrity and manufacturability. As high-frequency applications such as 5G millimetre-wave, satellite communications and autonomous driving become increasingly widespread, the use of PTFE PCBs is expanding, and the demands on routing design will only grow. Only by maintaining consistent impedance can the material advantages of PTFE be fully realised.
