The layer-up strategy for multilayer PCBs directly determines signal integrity, power supply stability and electromagnetic compatibility (EMC), and is a core skill that hardware engineers must master. A well-designed layer-up arrangement can suppress interference and enhance reliability at the lowest cost; conversely, it may lead to issues such as signal distortion and failure in EMC testing. Below, we outline the key considerations and pitfalls of layer design across five key areas: power and ground planes, signal isolation, analogue-digital partitioning, high-frequency layout, and priority allocation.
1.Power and Ground Planes: Laying the ‘Foundation’ for System Stability
The appropriate combination of power and ground planes forms the basis for ensuring power stability and signal integrity. The core objective is to minimise the area of the power loop and suppress power supply noise, thereby providing a clean and stable power supply environment for the system. In multilayer pcb design, the power plane must be closely adjacent to a continuous ground plane.
The capacitance formed between the two acts as a natural high-frequency decoupling capacitor, with a capacitance density reaching the 1 nF/cm² range. This effectively suppresses power supply noise at 100 MHz (with a suppression of approximately 0.1 V), significantly reducing the impact of power supply fluctuations on signal transmission.
In terms of layer sequencing, priority should be given to ensuring tight coupling between the power supply layer and the ground plane. Two classic structures are recommended:
SIG–GND–PWR–GND–SIG: Suitable for 6-layer and above pcb boards, this configuration effectively isolates the power supply layer from the signal layer using dual ground planes on both sides. It ensures the smallest possible power loop whilst providing excellent shielding for the signal layer, making it suitable for designs with high signal integrity and EMC requirements.
SIG–GND–PWR–SIG: Suitable only for 4 layer pcb boards. The spacing between the power plane and the ground plane must be strictly controlled to ensure the smallest possible power loop area, whilst avoiding interference caused by the signal layer being directly adjacent to the power layer.
It should be noted that the spacing between the power plane and the ground plane should not be excessive, as this would reduce the capacitance of the plane and weaken noise suppression capabilities; simultaneously, the ground plane should remain continuous, avoiding large-scale cut-outs or segmentation, to prevent noise being introduced by elongated power loops.
2.Signal Layer Isolation: Avoiding Interference and Ensuring Transmission Quality
The layout and isolation of signal layers directly affect signal transmission integrity, particularly for high-speed and sensitive signals. The core principle of layer design is that adjacent signal layers must be separated by a ground layer; a configuration where SIG1 and SIG2 are directly adjacent is strictly prohibited to prevent inter-layer crosstalk from affecting signal quality.
High-speed signals (data rates >500 Mbps, such as USB 3.0, PCIe, DDR, etc.): These should be routed on inner layers where possible, utilising the ground planes on either side to form a natural shield, effectively isolating external electromagnetic interference whilst reducing self-radiation. Measurements indicate that this approach can reduce signal radiation by more than 3 dB, significantly improving EMC performance. During routing, tight coupling with the ground plane is required to maintain transmission line impedance continuity and avoid reflections caused by vias, corners, or abrupt changes in trace width.
Low-speed signals (data rates <500 Mbps, such as GPIO, UART, etc.): These may be routed on the top layer or in remaining space on inner layers, but must be kept away from high-speed signals and power switching areas; the principle of the shortest path should also be followed to minimise delay and crosstalk.
3.Digital-Analogue Separation: Isolating Interference whilst Balancing Analogue and Digital Performance
In mixed-signal systems (which contain both digital and analogue circuits), digital-analogue separation is crucial. Switching noise and high-frequency interference from digital circuits can easily affect the accuracy and stability of analogue circuits; effective separation must be achieved through physical isolation and ground plane design.
The digital and analogue zones should be physically separated on the multilayer pcb,with a spacing of no less than 100 mil, filled with a ground plane to further isolate interference through shielding.
For mixed-signal systems subject to severe interference, an ‘island isolation’ strategy is recommended: a 20-mil isolation zone should be established between the digital and analogue zones, with no traces or components placed within this zone. Additionally, ferrite beads (or 0 Ω resistors) connecting the analogue ground to the digital ground should be positioned close to the ADC chip to minimise ground potential differences and ensure ADC conversion accuracy.
Furthermore, analogue and digital power supplies should be laid out separately, each corresponding to an independent power plane, to prevent digital power supply noise from coupling into the analogue power supply.
4.High-frequency signals: Specialised layout to meet GHz-level challenges
When signal frequencies reach the GHz range (such as RF signals and high-speed serial signals), the requirements for layer design become even more stringent. A ‘sandwich’ layer structure (SIG–GND–PWR–GND–SIG) is recommended, placing the GHz signals on the inner layers and utilising dual power supply layers and ground planes to form a Faraday cage. This provides all-round shielding, effectively isolating external interference and reducing transmission losses.
The impedance control accuracy of high-frequency transmission lines (such as microstrip lines) must be within ±5%, with a differential pair spacing error of less than 1 mil, to ensure the symmetry of differential signals and keep timing errors within 5 ps. Tracing lengths should be minimised wherever possible, avoiding excessively long vias and sharp bends; blind or buried vias should be prioritised to reduce reflections and losses. Additionally, high-frequency signal areas must be kept away from interference sources such as power switches and crystal oscillators.
5.Priority of Critical Networks: Rational Allocation of Resources
Different networks have varying impacts on system performance; therefore, priorities should be established to ensure the layout and routing of critical networks are safeguarded first, whilst allocating pcb board-layer resources rationally. Priorities, from highest to lowest, are as follows:
Power/Ground Networks: The core of the system’s power supply and interference shielding; low-impedance loops must be prioritised, with power planes and ground planes laid out first to minimise power supply noise.
High-Speed Clock/Differential Signals: These have extremely stringent requirements for timing and impedance; they should be routed on inner layers as a priority, with strict control over impedance continuity and timing accuracy.
Sensitive Analogue Signals (e.g., sensor signals, ADC inputs): These are highly susceptible to interference and should be kept away from switching power supplies and high-speed digital signals; they should be routed in the analogue region as a priority.
Low-Speed Control Signals: These have lower requirements and can utilise the remaining pcb board layer space, but must avoid cross-interference with critical signals.
Design Taboos and Classic Layering Recommendations
1.Design Taboos
On 4 layer pcb boards, the ‘jet-pack’ structure (SIG–PWR–SIG–GND) is prohibited: where the power layer is directly adjacent to the signal layer, power supply noise will couple directly into the signal layer, severely compromising signal integrity and EMC performance.
Avoid arbitrarily segmenting ground planes (especially continuous ground planes), as this lengthens power and signal loops, increasing interference and reflections.
High-speed or sensitive signals must not be placed adjacent to interference sources such as power switches or crystal oscillators.
2.Recommended Layering Schemes
Recommended for 6 layer pcb boards: TOP–GND–SIG–PWR–GND–BOT. This effectively isolates signal layers from power layers, with dual ground planes providing excellent shielding whilst ensuring minimal power loops. It is the preferred solution for balancing signal integrity, power stability and EMC performance, and is suitable for most mid-to-high-end hardware products.
For 10 layer pcb boards, the ‘3+3+4’ structure is preferred: 3 signal layers, 3 ground layers and 4 power layers. This meets the isolation and shielding requirements for multiple power domains and high-speed signals in complex systems (such as servers, industrial control equipment and high-end consumer electronics), significantly enhancing system reliability and immunity to interference.
The layering strategy for multilayer PCBs is crucial in determining signal integrity, power stability and EMC performance. By mastering the following core principles, you can effectively mitigate interference and improve design quality.
